The present invention relates to a memory device, and more particularly, to exemplary embodiments of a three dimensional memory device having stitched arrays of memory cells.
A resistance-based memory device normally comprises an array of memory cells, each of which includes a memory element and a selection element coupled in series between two electrodes. The selection element functions like a switch to direct current or voltage through the selected memory element coupled thereto. The selection element may be a three terminal device, such as transistor, or a two-terminal device, such as diode or Ovanic threshold switch. Upon application of an appropriate voltage or current to the selected memory element, the electrical property of the memory element would change accordingly, thereby switching the stored logic in the respective memory cell.
FIG. 1 is a schematic circuit diagram of a memory array 30, which comprises a plurality of memory cells 32 with each of the memory cells 32 including a two-terminal selection element 34 coupled to a resistance-based memory element 36 in series; a first plurality of parallel wiring lines 38 with each being coupled to a respective row of the memory elements 36 in a first direction; and a second plurality of parallel wiring lines 40 with each being coupled to a respective row of the selection elements 34 in a second direction substantially perpendicular to the first direction. Accordingly, the memory cells 32 are located at the cross points between the first and second plurality of wiring lines 38 and 40.
The resistance-based memory element 36 may be classified into at least one of several known groups based on its resistance switching mechanism. The memory element of Phase Change Random Access Memory (PCRAM) may comprise a phase change chalcogenide compound, which can switch between a resistive phase (amorphous or crystalline) and a conductive crystalline phase. The memory element of Conductive Bridging Random Access Memory (CBRAM) relies on the statistical bridging of metal rich precipitates therein for its switching mechanism. The memory element of CBRAM normally comprises a nominally insulating metal oxide material, which can switch to a lower electrical resistance state as the metal rich precipitates grow and link to form conductive paths upon application of an appropriate voltage. The memory element of Magnetic Random Access Memory (MRAM) typically comprises at least two layers of ferromagnetic materials with an insulating tunnel junction layer interposed therebetween. When a switching current is applied to the memory element of an MRAM device, one of the ferromagnetic layers will switch its magnetization direction with respect to that of the other magnetic layer, thereby changing the electrical resistance of the element.
A magnetic memory element normally includes a magnetic reference layer and a magnetic free layer with an electron tunnel junction layer interposed therebetween. The magnetic reference layer, the electron tunnel junction layer, and the magnetic free layer collectively form a magnetic tunneling junction (MTJ). Upon the application of an appropriate current through the MTJ, the magnetization direction of the magnetic free layer can be switched between two directions: parallel and anti-parallel with respect to the magnetization direction of the magnetic reference layer. The electron tunnel junction layer is normally made of an insulating material with a thickness ranging from a few to a few tens of angstroms. When the magnetization directions of the magnetic free and reference layers are substantially parallel or oriented in a same direction, electrons polarized by the magnetic reference layer can tunnel through the insulating tunnel junction layer, thereby decreasing the electrical resistance of the MTJ. Conversely, the electrical resistance of the MTJ is high when the magnetization directions of the magnetic reference and free layers are substantially anti-parallel or oriented in opposite directions. The stored logic in the magnetic memory element can be switched by changing the magnetization direction of the magnetic free layer between parallel and anti-parallel with respect to the magnetization direction of the reference layer. Therefore, the MTJ has two stable resistance states that allow the MTJ to serve as a non-volatile memory element.
Based on the relative orientation between the magnetic reference and free layers and the magnetization directions thereof, an MTJ can be classified into one of two types: in-plane MTJ, the magnetization directions of which lie substantially within planes parallel to the same layers, or perpendicular MTJ, the magnetization directions of which are substantially perpendicular to the layer planes.
The size of the memory array 30 illustrated FIG. 1 is often limited by the voltage drop caused by the parasitic resistance of the wiring lines 38 and 40, which may result in insufficient voltage or current to switch the selection element 34 or the memory element 36 or both. The convention approach to overcome the voltage drop issue is to increase the thickness of the wiring lines 38 and 40 in the vertical direction, thereby reducing the line resistance. However, as the width of the wiring lines 38 and 40 shrinks with progressive miniaturization of the memory cells 32, the thickness/width aspect ratio of the wiring lines 38 and 40 may become too high for the lines 38 and 40 to be reliably manufactured.
For the foregoing reason, there is a need for a memory device that has low voltage drop associated with its wiring lines and that can be inexpensively manufactured.